Digital receiver locking device

ABSTRACT

The invention relates generally to transmission of digitized information and more specifically to a digital receiver locking device that provides a decreased lock-in time and minimizes requirements to a permissible frequency and phase matching error. Outputs of a digital phase detector 1 are coupled, respectively, to an addition input of an analog adder 2 and a first information input of a multiplexer 3 having an output coupled to a subtraction input of the analog adder 2. An output of the adder 2 is connected via a low-pass filter to an input of a voltage controlled oscillator (VCO) 5 having an output connected to a clock input of a decision unit 6 whose information input is coupled, along with a first input of the phase detector 1 and a first input of a lock state detection circuit 7, to an input of the locking device. A second input of the phase detector 1 and a clock input of the decision unit 6 are coupled to an output of the VCO 5. A first output of the lock state detection circuit 7, which is an unlocked state indication output, is coupled to a control input of the multiplexer 3, and a second output of the circuit 7, which is a lock lead/lag indication output, is coupled to a second information input of the multiplexer 3.

FIELD OF THE INVENTION

The present invention relates generally to transmission of digitizedinformation and more specifically to a device for locking a receiver toa transmitter, using digital signal characteristics to control a phaseof a voltage controlled oscillator.

BACKGROUND OF THE INVENTION

It is known that a receiver can be locked by input data a through alocking device with a phase-locked loop (PLL) circuit including avoltage controlled oscillator. The oscillator signal is employed toclock the writing of input data to a locking device and to track theinput data at further transmission of the received signals to the otherapparatuses. The locked condition is achieved at definite limitations onthe initial matching error in phase and frequency of the voltagecontrolled oscillator (VCO) and input data (see F. M. Gardner. PhaselockTechnique. J. Wiley & Sons, 1979, ch.4). If initial frequency or/andphase values exceed permissible limits, the PLL circuit will not achievethe locked condition. To expand the range of the initial frequency andphase values at which the PLL circuit can be locked by input data, aforced variation of frequency and/or phase is employed.

In digital communication system receivers, the PLL circuit can be phaselocked to the VCO through the use, within the PLL circuit, of a phasedetector and a supplementary unit for forced scanning of the controlledoscillator frequency (see F. M. Gardner. Phaselock Technique. J. Wiley &Sons, 1979, ch.5) or an input signal phase (T. N. Lee, J. F.Bulzacchelly. 155 MHz Clock Recovery Delay-and-Phase-Locked Loop. IEEEJournal of Solid State Circuits, v.27, No.12, pp 1736-1745). With theprior art device, a locking band of the PLL circuit is expanded owing toa coarse frequency or phase lock during scanning.

Described in F. M. Gadner. Phaselock Technique. J. Wiley & Sons, 1979,ch.5, is a digital receiver locking device comprising a phase detectorand a decision unit, each one having inputs to which an informationsignal is provided, a VCO for generating a clock frequency for the phasedetector and the decision unit, a low-pass filter (LPF) having an inputcoupled to an output of the phase detector, an analog adder having oneinput coupled to an output of the LPF, another input coupled to asaw-tooth generator via a controllable switch, and an output coupled toa control input of the VCO, and a block information signal decoderhaving an input coupled to an output of the decision unit, and an outputcoupled to a control input of the switch. The saw-tooth generator, theswitch and the analog adder make up a frequency scanning unit.

In the above apparatus, a digital data signal is generated at the outputof the decision unit, and a clock frequency locked to the digital signalis generated at the output of the VCO. If a block lock condition issystematically lost, the decoder generates a scanning enable signal,responsive to which the switch connects an output of the saw-toothgenerator to an input of the adder. As the result, a saw-tooth voltageis generated at the adder output, causing a variation in the VCOgeneration frequency. Scanning of the VCO generation frequency isterminated when the decoder generates a control signal of appropriatelevel, that is provided to the switch.

A problem with the prior art locking device is a considerable time spentfor initial locking. The reason is that a short-term loss of the PLLlock condition may result in scanning a control signal in a directionopposite to the optimum one.

Closely approaching the claimed invention from the viewpoint oftechnical essence is a locking device comprising a digital phasedetector having a delay unit at an input and an analog adder at anoutput, a LPF and a VCO based on a quartz-crystal generator. An inputdata signal is provided to a first input of the delay unit, the delayeddata from an output of the delay unit are, in turn, provided to firstinputs of the phase detector and decision unit. From the LPF output, asignal is provided to a second control input of the delay unit. A signalof the VCO is provided to second inputs of the phase detector anddecision unit. The phase detector has several outputs of a first andsecond type. Averaged weighted amplitude values of pulses generated atthe inputs of the first and second type are used as the estimates of theVCO frequency lag and lead, respectively, relative to the input datafrequency. To obtain the estimates, the analog adder combinesappropriately weighted voltages generated at the first type outputs ofthe phase detector, and subtracts appropriately weighted voltagesgenerated at the second type outputs of the phase detector. An outputsignal of the analog adder is averaged by the LPF, the averaged signalbeing provided to control inputs of the VCO and delay unit. To lock theVCO by input data, the oscillator frequency should be equal to a codegeneration frequency. A digital signal is provided from an output of thedecision unit, and a clock frequency locked to the received digitalsignal is generated at the VCO output (see the aforementioned referenceof T. H. Lee, J. F. Bulzacchelly).

The prior art locking device, however, exhibits a narrow locking band ofthe PLL circuit, resulting in a necessity to use a VCO based on aquartz-crystal resonator.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a digital receiverlocking device that overcomes the aforementioned problems through adirectional scanning of the VCO frequency when the locked state is lost,until the lock-in condition is achieved. It ensures a decreased lock-intime and minimizes requirements to a minimum permissible phase andfrequency matching error.

The aforementioned technical result is attained by a first embodiment ofa digital receiver locking device comprising a digital phase detector,an analog adder having an addition input coupled to a first output ofthe phase detector, a low-pass filter having an input coupled to anoutput of the analog adder, a voltage controlled oscillator having aninput coupled to an output of the low-pass filter, and an output coupledto one input of the phase detector, another input of the phase detectorbeing coupled to an input of the digital receiver locking device, and adecision unit having an information input coupled to an input of thedigital receiver locking device, a clock input coupled to an output ofthe voltage controlled oscillator, and an output coupled to an output ofsaid digital receiver locking device, wherein in accordance with theinvention said digital receiver locking device comprises a two-inputmultiplexer having a first information input coupled to a second outputof the digital phase detector, and an output coupled to a subtractioninput of the analog adder, and lock state detection circuit having afirst input coupled to an input of the digital receiver locking device,a second input coupled to an output of the voltage controlledoscillator, a first output coupled to a control input of the two-inputmultiplexer, and a second output coupled to a second information inputof the two-input multiplexer.

The aforementioned technical result is further attained by a secondembodiment of a digital receiver locking device comprising a digitalphase detector, an analog adder having an addition input coupled to afirst output of the digital phase detector, a low-pass filter having aninput coupled to an output of the analog adder, a voltage controlledoscillator having an input coupled to an output of the low-pass filter,and an output coupled to one input of the digital phase detector,another input of the phase detector being coupled to an input of thedigital receiver locking device, and a decision unit having aninformation input coupled to an input of the digital receiver lockingdevice, a clock input coupled to an output of the voltage controlledoscillator, and an output coupled to an output of said digital receiverlocking device, wherein in accordance with the invention said digitalreceiver locking device further comprises a two-input multiplexer havinga first information input coupled to a second output of the digitalphase detector, and an output coupled to a subtraction input of theanalog adder, a lock state detection circuit having a first inputcoupled to an input of the digital receiver locking device and a secondinput coupled to an output of the voltage controlled oscillator, and adigital integrator having an information input coupled to a first outputof the lock state detection circuit, a clock input coupled to an inputof the digital receiver locking device, and an output coupled to acontrol input of the two-input multiplexer, a second output of the lockstate detection circuit being coupled to a second information input ofthe two-input multiplexer.

The digital integrator preferably comprises a shift register and anAND-gate having inputs coupled to information outputs of the shiftregister whose a clock input is coupled to a clock input of the digitalintegrator, an information input of the shift register being coupled toan information input of the digital integrator, and an output of theAND-gate being coupled to an output of the digital integrator.

The lock state detection circuit, both in the first and secondembodiments, preferably comprises a first, second, third and forthflip-flops, clock inputs of the first and second flip-flops beingcoupled to a second input of the lock state detection circuit, a directoutput of the first flip-flop being coupled to an information input ofthe second flip-flop having an inverse output coupled to an informationinput of the first flip-flop, a clock input of a third flip-flop beingcoupled to a first input of the lock state detection circuit, aninformation input of the third flip-flop being coupled to a directoutput of the second flip-flop, a direct output of the third flip-flopbeing coupled to a clock input of the forth flip-flop having aninformation input coupled to a direct output of the first flip-flop, aninverse output of the third flip-flop being coupled to a first output ofthe lock state detection circuit, and a direct output of the forthflip-flop being coupled to a second output of the lock state detectioncircuit.

In the digital receiver locking device in accordance with the invention,the lock state detection circuit continuously compares time of arrivalsof the falling edges of input data to the VCO signal. If the lockedstate is lost, said unit generates signals of an unlocked condition andlead/lag indication, by determining a relationship between the inputdata signal and VCO signal frequencies and phases. To perform thisfunction, an average VCO frequency is selected either equal to a doublecode generation frequency for input data having pulse falling edgescorresponding to the end or beginning of a clock interval, for example,for the NRZ signal, or equal to a code generation frequency for inputdata having pulse falling edges corresponding to the end of a clockinterval, for example, for the CMI signal. On generation of a high levelsignal indicating the loss of a locked condition, one of the phasedetector outputs is disabled and a constant level signal indicating thelock lead or lag is provided to the analog adder. The lead/lagindication signal level is set so as to correspond to a level of asignal at the output of the phase detector to which the multiplexer iscoupled. For example, if, on a lead, the phase detector generates a highaverage level, then said signal level should be also high and viceversa. When short pulses are present at the phase detector outputs and aconstant signal is provided to one of the analog adder inputs, the LPFintegrates the signal and generates a slowly increasing or decreasingcontrol voltage for the VCO, depending on whether the VCO signalfrequency and phase lag or lead those of input data. In this case, theVCO frequency is changing in a proper direction until a locked conditionis achieved.

If input data may contain noise, a digital integrator including a shiftregister and a gate is provided between the lock state detection circuitand the control input of the multiplexer. The gate generates a highlevel corresponding to an unlocked state indication and causing a VCOcontrol signal to be scanned when the shift register contains all"ones", and a low level in the opposite case. As the result, the impactof noise upon the stable operation of the PLL circuit including thephase detector, analog adder, LPF and VCO will be avoided.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be more clearly understood from the followingdetailed description of its embodiments, taken in conjunction with theaccompanying drawings in which

FIG. 1 is a block diagram of a first embodiment of a digital receiverlocking device in accordance with the present invention;

FIGS. 2a and 2b present diagrams of voltage distribution at inputs andoutputs of the digital receiver locking device units for the CMI inputdata signals;

FIG. 3 presents diagrams of voltage distribution at inputs and outputsof the digital receiver locking device units for the NRZ input datasignals;

FIG. 4 is a block diagram of a second embodiment of a digital receiverlocking device in accordance with the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIG. 1, a digital receiver locking device is shown ascomprising a digital phase detector 1 having outputs connected to anaddition input of an analog adder 2 and to a first information input ofa two-input multiplexer 3, respectively, an output of the two-inputmultiplexer being connected to a subtraction input of the analog adder2. An output of the adder 2 is coupled to an input of a LPF 4 whoseoutput is coupled to an input of a VCO 5. An output of the VCO 5 isconnected to a clock input of the decision unit 6 whose informationinput is coupled to an input of the digital receiver lock device, towhich also coupled are a first input of the phase detector 1 and a firstinput of a lock state detection circuit 7. A second input of the circuit7, a second input of the phase detector 1 and a clock input of thedecision unit 6 are coupled to an output of the VCO 5. A first output ofthe lock state detection circuit 7, which is an unlocked stateindication output, is coupled to a control input of a two-inputmultiplexer 3 having a second information input connected to a secondinput of the circuit 7, which is a lock lead/lag indication output.

As shown in FIG. 1, the lock state detection circuit 7 comprises a firstflip-flop 8, a second flip-flop 9, a third flip-flop 10 and a forthflip-flop 11, wherein the flip-flops 10, 11 are clocked by the pulsesignal falling edge, the flip-flop 8 is clocked by a high level, and theflip-flop 9 is clocked by a low level. Clock inputs of the first andsecond flip-flops 8,9 are connected to a second input of the lock statedetection circuit 7. A direct output of the first flip-flop 8 is coupledto an information input of the second flip-flop 9, an inverse output ofwhich is coupled to an information input of the first flip-flop 8. Aclock input of the third flip-flop 10 is coupled to a first input of thelock state detection circuit 7. An information input of the thirdflip-flop 10 is coupled to a direct input of the second flip-flop 9, anda direct output of the third flip-flop 10 is coupled to a clock input ofthe forth flip-flop 11 whose information input is connected to a directoutput of the first flip-flop 8. An inverse output of the thirdflip-flop 10 is coupled to a first output of the lock state detectioncircuit 7, and a direct output of the forth flip-flop 11 is coupled to asecond output of the lock state detection circuit.

An embodiment of a digital receiver locking device depicted in FIG. 4differs over the embodiment of FIG. 1 by the fact that it furthercomprises a digital integrator 12 having an information input coupled toa first output of the lock state detection circuit 7, a clock inputcoupled to an input of the locking device and an output connected to acontrol input of the two-input multiplexer. The digital integrator 12includes a shift register 13 with parallel outputs, that is clocked by arising edge of an input signal, and an AND-gate 14 generating a highlevel at the output thereof when the register 13 contains all "ones".Inputs of the AND-gate 14 are coupled, respectively, to informationoutputs of the shift register 13 having a clock input coupled to a clockinput of the digital integrator 12 and an information input coupled toan information input of the digital integrator 12, an output of theAND-gate 14 being coupled to an output of the digital integrator 12.

A digital receiver locking device operates as follows. Initially, when alock condition is absent, a phase of the VCO 5 signal "slips" relativeto a phase of an input data signal. At some point in time, "1" iswritten to the flip-flop 10 by the falling edge of the input datapulses, and then "0". This gives rise to generation of properly setlevels of lock state and lead/lag indication signals at a first andsecond outputs, respectively, of the lock state detection circuit 7. Tolock the VCO 5 by input data, there exists a definite relationshipbetween the input data and VCO signal frequency and phase: a fallingedge of the VCO signal clocks data so that the signal falling edge isaligned with the center of a data pulse. FIG. 2.a illustrates a properrelationship between phases of said signals when the input data is ofthe CMI format. The flip-flops 8 and 9 are connected by a frequencydivider scheme. An output signal of the flip-flop 9 is 90 degree shiftedrelative to an output signal of the flip-flop 8. Falling edges of theCMI signal are aligned with the center of the output signal pulse of theflip-flop 9. Therefore, in a locked condition, "1" is always written tothe flip-flop 10. If a phase of the VCO 5 signal leads the input datasignal, then, as shown in FIG. 2.b, at some point in time, "0" iswritten to the flip-flop 10 by the falling edge. Since in this case, asignal flock of the VCO 5 can not clock the data due to the edgemisalignment, the signal is no longer locked to the input data. If theinput data leads the signal of the VCO 5, "0" will be also written tothe flip-flop 10 by the falling edge. Therefore, a signal level at theoutput of the flip-flop 10 serves to monitor a lock state of the VCO 5signal and the input data, level "1" corresponding to a locked conditionand level "0" corresponding to an unlocked condition.

If before the lock is lost, "1" has been written to the flip-flop 10,"0" will be written when the locked condition is lost, and the flip-flop11 will generate a pulse at the clock output, by the falling edge ofwhich the information from the output of the flip-flop 8 will be writtento this flip-flop, particularly, "0" will be written if the VCO 5 signalleads the input data signal (FIG. 2.b) and "1" will be written if theVCO 5 signal phase lags the input data signal.

FIG. 3 illustrates a proper relationship between the VCO 5 signal andinput data phases for the NRZ signal. In this case, a generationfrequency of the VCO 5 is equal to a double code generation frequency.It follows from comparison of FIGS. 2b and 3 that the phase relationsfor the CMI data are also true for the NRZ data, i.e. the lock state(locked or unlocked) indication and lead/lag signals are generated atthe same phase relationships.

A direct or inverse lock indication signal is provided to an input ofthe multiplexer 3. In the embodiment depicted in FIG. 3, a signal fromthe inverse output of the flip-flop 10 is employed as a control signalin the multiplexer 3. In particular, if a low level is generated at theinverse output of the flip-flop 10, i.e. the device is in the lockedcondition, the phase detector 1 will be connected to the analog adder 2.But if a high level has been generated at the inverse output of theflip-flop 10, a constant level is provided from the flip-flop 11 to acorresponding input of the analog adder 2. As shown in FIG. 1, an outputof the multiplexer 3 is coupled to a subtraction input of the analogadder 2. From FIG. 2.b it follows that when the VCO 5 signal leads theinput data, a low level is generated at the output of the flip-flop 11.The LPF 4 converts the constant low level at the subtraction input ofthe analog adder 2 to a voltage increasing with time, that is applied asa control signal to the VCO 5 with the result that the VCO 5 frequencywill be decreased. If the VCO 5 frequency should increase with voltage,the inverse output of the flip-flop 11 is to be employed. Therefore,when the locked condition is lost, the VCO frequency is scanned so thatto eliminate the frequency and phase mismatch between the VCO 5 signaland input data. In a locked condition, (FIGS. 2.a and 3), the indicationsignal is inverted, and the second output of the phase detector 1 iscoupled to the subtraction input of the analog adder 2. With a minormatching error, the device maintains the locked condition only by theFLL circuit with a phase detector. The matching error being great, thelocked condition will be achieved after several iterations. In thelocked condition, input data is written to the decision unit 6, whereina signal from the VCO 5 is used as clock pulses. The data appears at theoutput of the decision unit 6 synchronously with the pulses of the VCO 5signal.

In-line noise can cause a false response of the locking device, whichresults in undesired scanning of the VCO 5 frequency. To avoid this, thelocking device can further comprise a digital integrator 12 (FIG. 4)based on a shift register 13 with parallel outputs, which is clocked bya rising edge of the input signal, and an AND gate 14 for generating ahigh level when the shift register 13 contains all "1's". In thisembodiment, the signal level required to start scanning the VCO 5frequency, that indicates an unlocked state, is generated when theunlocked state is repeatedly registered at the inverse output of theflip-flop 10. In order to reduce noise, a length of the shift register13 is selected with account of a probable maximum noise duration value.

Industrial Applicability

A digital receiver locking device in accordance with the presentinvention is applicable to synchronous digital communication systems.

We claim:
 1. A digital receiver locking device comprising:a digitalphase detector (1), an analog adder (2) having an addition input coupledto a first output of the phase detector (1), a low-pass filter (4)having an input coupled to an output of the analog adder (2), a voltagecontrolled oscillator (5) having an input coupled to an output of thelow-pass filter (4), and an output coupled to one of inputs of the phasedetector (1), another input of the phase detector being coupled to aninput of the digital receiver locking device, and a decision unit (6)having an information input coupled to an input of the digital receiverlocking device, a clock input coupled to an output of the voltagecontrolled oscillator (5), and an output coupled to an output of saidlocking device, said digital receiver locking device characterized inthat it further comprisesa two-input multiplexer (3) having a firstinformation input coupled to a second output of the digital phasedetector (1), and an output coupled to a subtraction input of the analogadder (2), and a lock state detection circuit (7) having a first inputcoupled to an input of the digital receiver locking device, a secondinput coupled to an output of the voltage controlled oscillator (5), afirst output coupled to a control input of the two-input multiplexer(3), and a second output coupled to a second information input of thetwo-input multiplexer (3).
 2. A device as set forth in claim 1, whereinthe lock state detection circuit (7) further comprisesa first flip-flop(8), second flip-flop(9), third flip-flop (10) and forth flip-flop (11),clock inputs of the first flip-flop (8) and second flip-flop (9) beingcoupled to a second input of the lock state detection circuit (7), adirect output of the first flip-flop (8) being coupled to an informationinput of the second flip-flop (9), whose inverse input is coupled to aninformation input of the first flip-flop (8), a clock input of a thirdflip-flop (10) being coupled to a first input of the lock statedetection circuit (7), an information input of the third flip-flop (10)being coupled to a direct output of the second flip-flop (9), a directoutput of the third flip-flop (10) being coupled to a clock input of theforth flip-flop (11), an information input of which is coupled to adirect output of the first flip-flop (8), an inverse output of the thirdflip-flop (10) being coupled to a first output of the clock statedetection circuit (7), and a direct output of the forth flip-flop (11)being coupled to a second output of the lock state detection circuit(7).
 3. A digital receiver locking device comprisinga digital phasedetector (1), an analog adder (2) having an addition input coupled to afirst output of the digital phase detector (1), a low-pass filter (4)having an input coupled to an output of the analog adder (2), a voltagecontrolled oscillator (5) having an input couped to an output of thelow-pass filter (4), and an output coupled to one of the inputs of thedigital phase detector (1), another input the phase detector beingcoupled to an input of the digital receiver locking device, and adecision unit (6) having an information input coupled to an input of thedigital receiver locking device, a clock input coupled to an output ofthe voltage controlled oscillator (5), and an output coupled to anoutput of said locking device, said digital receiver locking devicecharacterized in that it further comprisesa two-input multiplexer (3)having a first information input coupled to a second output of thedigital phase detector (1), and an output coupled to a subtraction inputof the analog adder (2), a lock state detection circuit (7) having afirst input coupled to an input of the digital receiver locking device,a second input coupled to an output of the voltage controlled oscillator(5), and a digital integrator (12) having an information input coupledto a first output of the lock state detection circuit (7), a clock inputcoupled to an input of the digital receiver locking device, and anoutput coupled to a control input of the two-input multiplexer (3), asecond output of the lock state detection circuit (7) being coupled to asecond information input of the two-input multiplexer (3).
 4. A deviceas set forth in claim 3, wherein the digital integrator (12) furthercomprisesan shift register (13) and an AND-gate (14) having inputscoupled to information outputs of the shift register (13), a clock inputof the shift register (13) being coupled to a clock input of the digitalintegrator (12), an information input of the shift register (13) beingcoupled to an information input of the digital integrator (12) and anoutput of the AND-gate (14) being coupled to an output of the digitalintegrator (12).
 5. A device as set forth in claim 3, wherein the lockstate detection circuit (7) further comprises a first flip-flop (8),second flip-flop (9), third flip-flop (10) and forth flip-flop (11),clock inputs of the first flip-flop (8) and second flip-flop (9) beingcoupled to a second input of the lock state detection circuit (7), adirect output of the first flip-flop (8) being coupled to an informationinput of the second flip-flop (9), whose inverse input is coupled to aninformation input of the first flip-flop (8), a clock input of a thirdflip-flop (10) being coupled to a first input of the lock statedetection circuit (7), an information input of the third flip-flop (10)being coupled to a direct output of the second flip-flop (9), a directoutput of the third flip-flop (10) being coupled to a clock input of theforth flip-flop (11), an information input of which is coupled to adirect output of the first flip-flop (8), an inverse output of the thirdflip-flop (10) being coupled to a first output of the clock statedetection circuit (7), and a direct output of the forth flip-flop (11)being coupled to a second output of the lock state detection circuit(7).
 6. A device as set forth in claim 4, wherein the lock statedetection circuit (7) further comprises a first flip-flop (8), secondflip-flop (9), third flip-flop (10) and forth flip-flop (11), clockinputs of the first flip-flop (8) and second flip-flop (9) being coupledto a second input of the lock state detection circuit (7), a directoutput of the first flip-flop (8) being coupled to an information inputof the second flip-flop (9), whose inverse input is coupled to aninformation input of the first flip-flop (8), a clock input of aflip-flop (10) being coupled to a first input of the lock statedetection circuit (7), an information input of the third flip-flop (10)being coupled to a direct output of the second flip-flop (9), a directoutput of the third flip-flop (10) being coupled to a clock input of theforth flip-flop (11), an information input of which is coupled to adirect output of the first flip-flop (8), an inverse output of the thirdflip-flop (10) being coupled to a first output of the clock statedetection circuit (7), and a direct output of the forth flip-flop (11)being coupled to a second output of the lock state detection circuit(7).